Integrated circuits are often tested using a number of structured design-for-testability (DFT) techniques. These techniques rest on the general concept of making all or some state variables in the design under test (e.g., sequential elements, such as flip-flops, latches, and other memory elements) directly controllable and observable. If this can be arranged, a circuit can be treated, as far as the testing of combinational faults is concerned, as a combinational or a nearly combinational network.
One of the most-often-used DFT methodologies is based on scan chains. Scan-based testing assumes that during testing all (or almost all) sequential elements in the circuit design can be connected into one or more shift registers. A circuit that has been designed for scan-based testing typically has two modes of operation: a normal mode and a test (or scan) mode. In the normal mode, the memory elements perform their regular functions. In the scan mode, the sequential elements become “scan cells” that are connected to form a number of shift registers called “scan chains.” These scan chains are used to shift a set of test patterns into the circuit and to shift out circuit responses to the test patterns (the test responses) after the circuit has been operated for one or more cycles in its normal mode. The test responses are then compared to fault-free responses to determine if the circuit under test (CUT) works properly.
Some DFT techniques use compactors to compress test responses unloaded from scan chains. Among the various types of compactors that can be used are so-called “time compactors.” Time compactors typically comprise a feedback structure with two or more feedback loops and two or more sequential elements for storing a “signature” that represents the results of a test. After a signature is generated by the time compactor (e.g., after a full test response to a test pattern is clocked into the time compactor), the signature can be output and compared to a fault-free signature to determine if an error exists in the circuit. Among the most popular time compactors used in practice are linear feedback shift registers (LFSRs). In one basic form, a type I LFSR is modified to accept a single external input in order to act as a polynomial divider. An example of such a modified type-1 LFSR is shown as compactor 100 in FIG. 1. As shown by compactor 200 in FIG. 2, a type II LFSR can be similarly modified. In both exemplary compactors 100, 200, the input sequence, represented by a polynomial, is divided by the characteristic polynomial of the LFSR. As the division proceeds, the quotient sequence appears at the output of the LFSR and the remainder is kept in the LFSR. Once testing is completed, the content of the LFSR can be treated as the signature.
FIG. 3 shows an example 300 of another time compactor called a multiple-input LFSR, which is also known as a multiple-input signature register (MISR). A MISR is often used to test circuits having multiple scan chains. MISRs also feature a number of logic gates between the flip-flops of the shift register into which test response bits from the scan chains can be input (e.g., XOR or XNOR gates).
One desirable characteristic of any compactor is an ability to detect multiple errors (that is, two or more errors) that are present in a given test response. For example, if two faulty test response bits are unloaded from the scan chains of a circuit-under-test, the signature produced by a time compactor desirably indicates the presence of the errors in the circuit-under-test. Such detection, however, can be difficult in a time compactor on account of the feedback structure, which creates the possibility for a first error to be cancelled-out or “aliased” by a second error, thus producing a fault-free signature. Another desirable characteristic of a compactor is the ability to diagnosis errors in a circuit-under-test (e.g., to help identify or to specifically identify failing scan cells). The ability of a compactor to achieve these two characteristics can be affected by the presence of one or more unknown states in the test response (also referred to as “X states” or “X values”), which can mask a faulty test response bit and produce a non-faulty signature. Furthermore, as circuit designs and testing techniques become more complex, the ability of a compactor to tolerate unknown (or X) states is becoming increasingly important. For example, in addition to the traditional sources of X values (e.g., non-scan flip-flops, floating buses, un-initialized memory elements, design black boxes, or artifacts of clock interaction in test mode) so-called “at-speed testing” can introduce false and multi-cycle paths that also result in unknown states. Because X values are becoming more and more ubiquitous and are generally difficult to eliminate, a time compactor desirably has some ability to tolerate one or more X states.
Accordingly, there is a need for an improved time compactor and related methods.